FPGA Engineer
Hautcharage
(Luxembourg)
Available
Key responsibilities
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Design complexes HDL systems, including SoC
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Design and implement complex IP from scratch
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Integrate existing IP and HDL code in new design
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Define functional and performance goals with the software team
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Develop designs and define micro-architecture plans for specifications review and test bench plans.
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Optimize synthesis/place&route for timing optimization
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Demonstrate best-practice design methodologies to achieve reliable and high-speed designs
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Manage deliverables to meet the project requirements
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Define HDL unit requirements from functional needs
According to profile
Job requirements
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VHDL and/or Verilog
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Low level HDL implementation (clock domain, core FPGA primitives)
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CPU, SoC architecture/design and industry standard interfaces.
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FPGA tool flows: synthesis, partitioning, place & route: ISE, Vivado, etc.
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FPGA partitioning and constraining of synthesis; Design optimizations with respect to FPGA limitations
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Familiarity with the latest Xilinx FPGA technologies such as 7 series or Ultrascale+
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Master degree in electronics engineering or equivalent
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Over 5 years relevant experience required
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Fluent in English, French is a plus as well as other languages
Preferred skills
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In scripting/programming - ideally Unix, Tcl, C, C++ including low-level programming (firmware)
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Embedded Linux
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MATLAB/Simulink, and Hardware-in-the-Loop simulation
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Hardware/system design, tools, debug, lab experience and vendor interface